Butterfly
Sandeep

πŸ‘‹ Sandeep is passionate about high-performance accelerated computing on GPUs using CUDA, leveraging NVIDIA's parallel programming platform. He is also deeply involved in competitive programming 🧩 and regularly participates in contests while solving data structures and algorithms problems πŸ’». He enjoys working on exciting projects and is always open to collaboration 🀝. Feel free to reach out if you'd like to work with him! He has recently completed his undergraduate degree in Computer Science and Engineering from IIT Palakkad. πŸŽ“

Skills

C, C++
Python
PostgreSQL
NodeJS
VHDL
Git
DSA
GitLab CI/CD
GPU Programming (CUDA C++)
Competitive Programming

Ongoing Research

GPU Programming: Accelerating Algorithms with Parallelism

Our research focuses on accelerating well-known algorithms by harnessing the power of GPU parallelism. We are optimizing reduction operations for large arrays (size β‰₯ 108) using CUDA programming, achieving an 18% speedup compared to NVIDIA's Thrust library. These gains come from innovative strategies we're excited to publish in upcoming papers. πŸ“„

Current work includes optimizing SSSP implementations on GPUs (static and dynamic settings) and advancing the PageRank algorithm through high-performance computing techniques. πŸ’‘

Part I: Core Foundations

GPGPU SIMT SIMD PageRank Reduction Thrust CSR PageRankContribution(PRC) Sequential Consistency

Part II: Advanced Implementations

GPGPU SIMT SSSP Thrust/CUB Static/Dynamic Graphs Sparse/Dense Graphs Coarse/Fine-grained Parallelism Grid/Block/Warp-strides Memory/Execution Analysis Edge List/CSR/Adjacency Lists Reduction Dot Product Norms Warp Level Primitives

Projects

Octopus: A Mini GitHub Version Control Platform

Cloud-based collaboration platform with version control and user management features.

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Skip List in C++

An optimized Skip List data structure in C++, designed to outperform std::set for certain operations.

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RISC-V Processor

Designed and implemented a 5-stage RISC-V processor using Verilog.

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Case Study: Random Graph Models vs Real Networks

Compared the properties of random graph models like the ER (ErdΕ‘s–RΓ©nyi) and BA (BarabΓ‘si–Albert) models with real-world networks such as Facebook.

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View Presentation

Chip Design for: 24 Hr Clock and Alarm

Using FPGA and Verilog, designed a chip for a 24-hour clock and alarm system with a Zybo board, LEDs, and logic gates.

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AI Spam Filter

Built a spam filter using a probabilistic approach with a naive Bayes classifier, trained on data to accurately detect spam messages.

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